Flip Chip Rework

From ACI Technologies

Flip Chip Rework

Flip chip components have been gaining popularity in the electronics industry since their introduction in the 1960s. Recent advances in attach methods and adhesives, as well as the drive for smaller and faster electronic devices have made the technology take off. The basic premise of the flip chip is that the chip (semiconductor device) is mounted flipped from the traditional position. The traditional method of mounting a die is to mount it on a lead frame with the circuit and bond pads face up. The bond pads then receive a bond wire which then connects to the proper lead on the lead frame. Flip chips are mounted face down onto a substrate using small bumps on the bond pads to make direct electrical connection to their respective pads on the substrate. Stay tuned for more information on attachment techniques next month. This article will focus on how to rework flip chips.

All types of underfill and adhesives have varying setting temperatures and rework temperatures. The techniques described below are applicable for the generic types of flip chip bonds. Follow your specific manufacturer instructions for optimizing rework results.

Reflow Solder Flip Chip Removal

The simplest flip chips to rework are those that have been attached using solder bumps. These chips are installed in a similar fashion to standard surface mount technology (SMT) components. If testing proves that a flip chip needs to be reworked prior to underfill, the removal process is the same as that of an SMT component. Simply apply flux and heated gas to both the chip and substrate to bring the assembly to 10-20 degrees C above the melting point of the solder and remove the flip chip with a vacuum removal tool. Once the flip chip has been removed, carefully remove all excess solder from the mounting pads. Clean the area thoroughly and inspect the substrate to ensure that it has not been damaged. Reattach a new flip chip.

If the chip already has been underfilled, rework is dependent on the type of underfill. The bond of most epoxy underfills can be broken utilizing heat. Some epoxies have solvents that reduce the heat needed to break the adhesion, but the tradeoff is the time that it takes for the solvent to break down the epoxy. Heat the area with hot gas according to the manufacturer's rework profile and remove the chip with a sliding motion. Remove any epoxy residue with the appropriate solvent, clean the substrate and attach a new chip. Some examples of flip chip rework stations are shown in Figure 1.



Figure 1: Examples of flip chip rework stations. Features for flip chip rework include placement accuracy of better than 10 microns and precision thermal management.

Adhesive Flip Chip Removal

Another method of flip chip attach uses adhesives, Anisotropic Conductive Film (ACF), Isotropic Conductive Adhesive (ICA), or Non Conductive Adhesive (NCA). Many of these adhesives can be softened by heating. The manufacturer’s data sheet will typically show a “Tacking Condition” where the adhesive begins to get tacky and a "Bonding Condition", which shows the temperature, pressure, and time needed for the adhesive to actually form a reliable bond. Some adhesives can be reworked at the Tacking Condition temperature, while others need to be heated to the Bonding Condition temperature. Again, consult the manufacturer's data sheet for rework activation temperatures and recommended solvents for cleaning the bond area prior to setting a new flip chip.

If the assembly cannot withstand the heat prescribed in the manufacturer’s specifications for rework, a solvent may be used to break down the adhesive at a lower temperature. Before using a solvent the engineer must verify that all components can withstand exposure to the solvent without any degradation. This solvent may be either applied to the general area of the flip chip or the entire substrate may be submerged in a solvent bath. As with reflow underfill, the tradeoff for lowering the temperature of rework is the time that the solvent will take to dissolve the adhesive bond. This time is typically 8-24 hours.

Thermosonic and Thermocompression Flip Chip Removal

Both of these methods of flip chip attach create extremely strong inter-metallic bonds at the chip to substrate interface. There are no rework processes that can be recommended that will not damage the substrate pad when attempting to remove a flip chip that has been attached with either thermosonic or thermocompression assembly techniques.

In summary, most of the more common production methods of attaching flip chips can be reworked. The keys to successful removal are to know which method of attaching the chip and substrate has been used, know which adhesives or epoxies were used, and follow the manufacturer’s instructions for removal. In the process of flip chip rework, a little research can go a long way.

For further information regarding flip chip rework, please contact ACI Technologies at 610.362.1320 or via email at helpline@aci.org.

ACI Technologies, Inc.

Conformal Coating Inspection

From ACI Technologies



In the field of electronics manufacturing, the end use of the product will always dictate the processes, procedures, and methods, not only for building the product, but also for testing, cleaning, and protecting the assembly in order to assure the level of quality required for proper operation. The need to protect an electronic assembly from its end use environment may stem from any one of a number of hazardous (or potentially hazardous) conditions. Choosing the type of protective material is dependent upon matching that material's characteristics with the conditions to be overcome. Naturally, the use of a protective (conformal) coating will require some method of verification to ensure the desired level and type of protection is achieved.

There are a variety of reference documents providing specifications for conformal coatings. The intent of this article is to give an overview of inspection methods and considerations when using such coatings in the course of manufacturing an electrical or electronic product.

The five general categories of conformal coatings are:

• Type AR-Acrylic Resin
• Type ER-Epoxy Resin
• Type SR-Silicone Resin
• Type UR-Polyurethane Resin
• Type XY-Paraxylylene (also referred to as Parylene)

When establishing manufacturing processes which includes the application of a conformal coating, it is recommended that the coating be qualified in regards to physical characteristics including (but not limited to), shelf life, cure time, viscosity, fungus resistance, flexibility, flammability, dielectric withstanding voltage, and thermal shock.1 (Note: for details on verification methods of the above characteristics consult IPC-TM-650, ASTM D-1084, and UL 94 HB.)

Once the type of coating has been established, qualified, and incorporated into a process, it is necessary to continually verify quality conformance. It is important to check the material for physical appearance, fluorescence, thickness, and full cure.

The IPC J-STD-001D specifies that conformal coatings must be fully cured and homogeneous. Also, because the intent of conformal coating is to provide an immediate barrier to a harsh environment, the standard specifies that conformal coating must be free of blisters, breaks, cracks, voids bubbles, mealing, peeling, wrinkles, or foreign material which would expose conductive surfaces to the environment.2 Physical appearance can be easily verified by visual inspection. Magnification may be used up to 4X.

When conformal coatings contain a UV tracer (dye), inspection can be performed using an ultraviolet (UV) light source (Figure 1). This becomes a valuable tool for verifying complete coverage and any specified areas that should be free of conformal coating (such as electrical contacts).


Figure 1: Image of a board under UV illumination with conformal coating only on the lower portion (purple area).

The specifications for thickness of a conformal coating vary depending upon the type of coating used. The J-STD-001D specifies 0.03-0.13 mm for types AR, ER, and UR, but requires a thicker coverage of 0.05-0.21 mm for SR types. Because it is the most resilient, Paraxylylene is only required to have a thickness of 0.01-0.05 mm.3

The thickness of the coating can be measured in a number of ways, but most of the methods used fall into one of two general categories.

1. Dry film method: Measurement using a micrometer (or indicator accurate to 12.5 ± 2.5µm)4, made on a test coupon of the same type of material as the printed board or may be of a nonporous material such as metal or glass. Such measurements are to be made on a flat, unencumbered, fully cured surface of the printed circuit assembly or a test coupon.5
2. Wet film method: This alternative method measures the coating while it is still wet (before curing has been completed) and provides for calculations that will indicate the thickness after curing has been completed. This method is preferred when a dry film method is not practical or would be destructive.

For more details on methods and processes regarding the application and measurement of conformal coatings, ACI Technologies offers the IPC J-STD-001D course, as well as the IPC 7711/7721 Rework and Repair course. Please contact the Registrar at 610.362.1295 or visit our website at www.aciusa.org/courses.

References

1. Qualification and Performance of Electrical Insulating Compound for Printed Wiring Assemblies. IPC-CC-830B. Association Connecting Electronics Industries. Table 3-1.
2. Requirements for Soldered Electrical and Electronic Assemblies. ANSI/IPC J-STD-001D. Association Connecting Electronics Industries. Clause 10.1.2.2.
3. Ibid. Clause 10.1.2.1.
4. IPC-CC-830B. op.cit. Clause 4.7.4.
5. ANSI/IPC J-STD-001D. op.cit. Clause 10.1.2.1.

Ross Dillman
Technician/Instructor
ACI Technologies, Inc.

ACI Technologies, Inc. 2013 Training Update

From ACI Technologies, Inc.

For detailed course descriptions and online registration, visit ACI Technologies, Inc. Online Store.

For the complete article, visit www.aciusa.org

Solder Tips from ACI Technologies

From ACI Technologies, Inc.

Flip Chip Assembly
The intense competition in the electronics industry generally serves to drive down the size and cost of electronic products while improving their performance, flexibility, and reliability. As a part of this effort, packaging methods are constantly being improved and new, innovative methods are being developed. One area of focus is highly integrated chip-level electronics assembly, using multiple unpackaged dies and electrical components in a single package. One of the most popular methods is known as flip chip assembly.

Flip chip microelectronic assembly is the direct electrical connection of face-down, or flipped electronic components onto substrates, circuit boards, or carriers, by means of conductive bumps on the chip input/output (I/O) pads. In contrast, wire bonding uses face-up chips with a wire connection to each pad (Figure 1-1). Flip chip components are predominantly semiconductor devices; however, components such as passive filters, detector arrays, and microelectromechanical systems (MEMS) devices are also used in flip chip form. IBM still uses the flip chip interconnection that they introduced in the early sixties for their mainframe computers. The assembly process has proliferated in many other applications, including automotive electronics, smart cards, radio frequency identification (RFID) cards, electronic watches, cell phones, and high speed microprocessors.

Figure 1-1: Wire bond versus flip chip

The popularity of flip chip packaging results both from flip chip's advantages in size, performance, flexibility, reliability, and cost over other packaging methods and from the increased availability of flip chip materials, equipment, and services. Eliminating package molding and bond wires reduces the required board area by up to 95%, and requires far less height. Flip chip offers the highest speed electrical performance of any assembly method due to reduced signal inductance. This is because the interconnection path is much shorter in length (0.1mm versus 1-5mm) greatly reducing the inductance of the signal path. Additionally, the power to ground inductance is reduced. By using flip chip interconnection, power can be brought directly into the core of the die, rather than having to be routed to the edges. This greatly decreases the noise of the core power, improving performance of the silicon. This is a key factor in high speed communication and switching devices and gives good I/O connection flexibility. A higher signal density is available with flip chip assembly. The entire surface of the die can be used for interconnect, rather than just the edges. Since a flipped chip can connect over the surface of the die, it can support vastly larger numbers of interconnects for a given die size. For a die where size is determined by the edge space required for bond pad ("pad limited") the size of the die can be reduced, saving silicon cost. In some cases, the total package size can be reduced using flip chip. This can be achieved by either reducing the die to package edge requirements, since no extra space is required for wires, or in utilizing higher density substrate technology, which allows for reduced package pitch. Flip chip assembly is a mechanically rugged interconnection method when completed with an adhesive underfill. This method also has the lowest cost interconnection for high volume automated production.

There are three stages in making flip chip assemblies: bumping the die or wafer, attaching the bumped die to the board or substrate, and in most cases, filling the remaining space under the die with an electrically non-conductive material. The conductive bump, the attachment materials, and the processes used differentiate the various kinds of flip chip assemblies. The most common bumping and attaching methods include solder bump, plated bump, stud bump, and adhesive bump. The bump serves several functions in the flip chip assembly. Electrically, the bump provides the conductive path from chip to substrate. The bump also provides a thermally conductive path to carry heat from the chip to the substrate. In addition, the bump provides part of the mechanical mounting of the die to the substrate. Finally, the bump provides a spacer, preventing electrical contact between the chip and substrate conductors, and acting as a short lead to relieve mechanical strain between board and substrate.

The cost, performance, and space constraints of the application determine which method is the most suitable. A current EMPF project is focused on the development of a silicon germanium (SiGe) System on a Chip (SoC), assembled in a Flip Chip on Board (FCoB) configuration. For SiGe applications, stud bump bonding is considered to be one of the most robust packaging options given the process restrictions. The balance of this article reviews some of the more common bump attachment methods.

Solder Bump Flip Chip

The solder bumping process first requires that an under bump metallization (UBM) be applied to the aluminum chip bond pads, typically by sputtering or plating to remove the insulating oxide layer and to define the solderable area. Solder is deposited (Figure 1-2) on the UBM by needle-depositing or screen printing solder paste, evaporation, or electroplating. After solder bumping, the wafer is cut into bumped die. The bumped dies are placed on the substrate pads, and the assembly is heated to make a solder connection.

Figure 1-2: Solder balls.

Stud Bump Flip Chip

The gold stud bump flip chip process, bumps die by a modified standard wire bonding technique. This technique makes a gold ball for wire bonding by melting the end of a gold wire to form a sphere. The gold ball is attached to the chip bond pad as the first part of a wire bond. To form gold bumps instead of wire bonds, modified wire bonders break off the wire after attaching the ball to the chip bond pad. The gold stud bump remaining on the bond pad provides a permanent connection through the aluminum oxide to the underlying metal. Gold stud bump flip chips may be attached to the substrate bond pads with conductive adhesive (Figure 1-3) or by thermosonic gold-to-gold connection.

Figure 1-3: Double stud bump attached with conductive epoxy.

Plated Bump Flip Chip

Plated bump flip chip uses wet chemical processes to remove the insulating oxide layer and plate conductive metal bumps onto the wafer's aluminum bond pads. In general, plated nickel-gold bumps are formed on the semiconductor wafer by electroless nickel plating of the aluminum bond pads of the chips. After plating the desired thickness of nickel, an immersion gold layer is added for protection, and the wafer is cut into bumped die. Alternatively, silver bumps are electroplated on a sputter seeded semiconductor wafer (Figure 1-4). Attachment generally is by solder or adhesive, which may be applied to the bumps or the substrate bond pads by various techniques.

Figure 1-4: Silver plated bumps.

Adhesive or Polymer Bump Flip Chip

The polymer bump process is a patented, stencil printing technology in which isotropically conductive, silver filled polymers are printed through metal stencils to form polymer bumps on a zincate-nickel gold, electroless plated UBM that covers the aluminum bond pads of the semiconductor die. The polymers are either thermoset which cures with heat, or thermoplastic which softens with heat. These silver-filled polymers are formulated for high precision stencil printing through laser etched or electroformed metal stencils. Once the bumped wafers are diced, the chips are inverted and bonded to the substrate. Final processing involves a heat cure for the thermoset bumps while the thermoplastic bump connections are made in a few seconds as heat and pressure are used to melt the thermoplastic.

Flip Chip Underfill

As described above, one function of the bump is to provide a space between the chip and the board. In the final stage of assembly, this under-chip space is usually filled with a non-conductive "underfill" adhesive joining the entire surface of the chip to the substrate.

The underfill protects the bumps from moisture or other environmental hazards, and provides additional mechanical strength to the assembly. However, its most important purpose is to compensate for any thermal expansion difference between the chip and the substrate. Underfill mechanically "locks together" chip and substrate so that differences in thermal expansion do not break or damage the electrical connection of the bumps.

Underfill may be needle-dispensed or jet-dispensed along the edges of each chip. It is drawn into the under-chip space by capillary action and heat-cured to form a permanent bond.

Conclusion

The methods covered in this article are only a few of the wide range of techniques used as part of the flip chip process. The development of new techniques is proceeding continually. Flip chip assembly has been shown to have significant advantages over other microelectronic packaging methods. Several varieties of flip chip assembly, including solder bump, plated bump, gold stud bump, and adhesive bump are suitable for a wide range of applications.

ACI Technologies, Inc.

ACI Technologies Featured Workshop: Stick With Quality Adhesive Technologies

From ACI Technologies

Stick With Quality Adhesive Technologies

Presented by Henkel, manufacturer of Loctite brand products

Learn the latest technologies available for designing and assembling components with adhesives at this free workshop. Gain an understanding of the various processes, including advantages and limitations; ascertain the essential considerations for choosing the best adhesive solution.

Experience hands-on adhesive demonstrations, see dispensing and curing equipment in action and participate in an informative question and answer session. Topics will include visible light cure, anaerobic, hot melt, two-part silicone, instant adhesive and structural adhesive technologies.

Bring your parts, prints and problems with you. Engineering and technical representatives will be available after the forum for one-on-one discussions and demonstrations. We'll study your specific application and suggest new and improved methods, solve your toughest assembly issues, or help you in any way we can without cost or obligation.

Industry finds solutions to its biggest challenges with quality Loctite products from Henkel. These products, services and applications can make your life easier and help improve your company's bottom line.

Date: Wednesday, October 10, 2012  
Time: 9:00am - 4:00pm with complimentary lunch
RSVP: Katie Riggan by phone at 610.362.1200, extension 250 or via email at registrar@aciusa.org Location: ACI Technologies, Inc.
1 International Plaza, Suite 600
Philadelphia, PA 19113
ACI is located adjacent to the Philadelphia airport with free parking. Visit ACI on the web at www.aciusa.org.

ACI Technologies, Inc. Upcoming Courses

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